Senior Validation Engineer at Microsoft
Duration: April 2022 to Present
Core and Mesh Validation: Played a pivotal role in validating the core and mesh in Microsoft's custom silicon, ensuring the reliability and performance of these critical components.
Cobalt100 SoC Launch: Contributed significantly to the successful launch of the first SoC for data centers, known as Cobalt100. This project involved validating the ARM Perceus Core (Neoverse N2).
Test Plan Development: Developed comprehensive test plans and content to validate Core and Mesh IP, utilizing programming languages such as C/C++ and Python.
Technical Expertise: Leveraged advanced validation techniques and tools to ensure the robustness and efficiency of Microsoft's custom silicon designs.
Verification Validation Engineer at Intel
Duration: Sept 2013 to Apr 2022
HVM Functional Test Writer: Developed high-volume manufacturing (HVM) functional tests to enhance coverage for x86 cores, targeting specific test holes based on system-level silicon feedback.
Core Test Coverage Analysis: Conducted thorough analysis of core test coverage, identifying gaps and writing content to effectively target them. This involved studying collaterals, micro-architecture, and RTL.
Simulation Time Optimization: Led a cross-organizational effort to reduce simulation time by 80% through a carefully crafted save & restore technique. This initiative earned you an “Org Level Excellence Award.”
Silicon Bring-Up Support: Actively participated in silicon bring-up, supporting core-specific tasks and queries, and finalizing core-specific fuses for test content.
Defect Screening: Developed tests to screen out defects encountered by customers, addressing test holes and ensuring the integration of these tests into the test program.
Zoix Model Build and Fault Grade Content: Built Zoix models and fault-graded content to obtain coverage numbers, analyzing the effectiveness of coverage metrics in relation to real silicon defects.
Cross-Team Collaboration: Worked collaboratively with peers across teams to check the effectiveness of developed content and integrate it into the test program.
Graduate Research Assistant at PROACTIVE Lab, Virginia Tech
Duration: Jan 2013 to Apr 2022
During my time as a Graduate Research Assistant at the PROACTIVE Lab at Virginia Tech, I focused on developing methods for trusted hardware implementation to enhance the security of integrated circuits (ICs). My research aimed to address critical issues related to tampering, reverse engineering, and counterfeiting of ICs.
More details about my research can be found here: Research Contributions
Graduate Technical Intern at Intel
Duration: Jan 2012 to Aug 2013
During my internship at Intel, I worked on developing an Electronic Design Automation (EDA) tool for fault diagnosis using an architectural simulator. This experience provided me with valuable insights into the practical applications of my academic knowledge and allowed me to contribute to a significant project within the company.
Key Contributions:
1) EDA Tool Development:
- I was involved in the development of an EDA tool designed for fault diagnosis. This tool utilized an architectural simulator to identify and diagnose faults in integrated circuits (ICs).
- My role included designing and implementing various components of the tool, ensuring its accuracy and efficiency in diagnosing faults.
2) Collaboration and Teamwork:
- I collaborated with a team of engineers and researchers, contributing to brainstorming sessions and technical discussions to enhance the tool's capabilities.
- This experience helped me develop strong teamwork and communication skills, as I worked closely with colleagues to achieve common goals.